Although applicable, in principle, to any desired integrated circuits, the present invention and also the problem area on which it is based are explained with regard to memory cell semiconductor structures with trench capacitors in silicon technology.
FIG. 2 shows conventional memory cell semiconductor structures with trench capacitors in silicon technology, which is also referred to as an MINT cell layout.
In FIG. 2, reference symbols G1 to G8 designate trench capacitors which are arranged offset relative to one another in pairs in rows and columns. Lying between the trench capacitors G1 to G8 are active regions AA1 to AA7 or shallow trench isolation structures STI filled with an insulation material, which enclose the active regions AA1 to AA7 in insular fashion.
Accommodated in the active regions AA1 to AA7 are respective selection transistors (not shown) for the trench capacitors G1 to G8. In this case, the selection transistors of in each case two trench capacitors, for example G4 and G5 have a common bit line terminal lying approximately in the center of the active region, in this case AA4. Situated between the bit line terminal and the respective trench capacitor is a gate line terminal connected to a respective word line. In the case of the present layout, the bit lines (not shown) run in the row direction and the word lines (not shown) run in the column direction. The cells are configured symmetrically with respect to the common bit line terminal.
Filling the isolation trench structure with the insulating filling material, which is generally composed of silicon oxide, has proved to be problematic in case of such an arrangement scheme for a memory cell semiconductor structure with trench capacitors. This is because the structures have a high aspect ratio in particular in the isolation trenches between the adjacent rows, which generally has the effect that shrink holes form in the insulating filling material. It is primarily at the location at which two adjacent active regions overlap that the aspect ratio of the STI trench to be filled is very high and the risk of shrink hole formation is thus the greatest.
Usually, the shrink hole formation can only be avoided by carrying out multiple deposition and wet-chemical etching-back of the insulating filling material.
The present invention provides an improved method for fabricating such a semiconductor structure which makes it possible to reduce the risk of shrink hole formation during filling of the isolation trenches.
Advantages of the fabrication method according to the invention are, in particular, that the aspect ratio can be relaxed in the critical overlap region and regions with a particularly critical aspect ratio are eliminated or can at least be greatly reduced in size. The risk of shrink hole formation during filling of the isolation trenches is reduced from the outset in this way.
The process results in reduction or elimination of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process.
In accordance with one preferred embodiment, the trenches each have a trench capacitor with a corresponding filling, which is sunk with respect to the top side of the semiconductor substrate.
In accordance with a further preferred embodiment, the receding process is realized by an isotropic, preferably wet-chemical, etching process, as a result of which the thickness of the hard mask that has been caused to recede is reduced in comparison with the thickness of the hard mask. The aspect ratio can be configured even more favorably as a result.
In accordance with a further preferred embodiment, the first hard mask is composed of silicon nitride.
In accordance with a further preferred embodiment, the second hard mask is composed of silicon oxide.
In accordance with a further preferred embodiment, the filling material is composed of silicon oxide.
In accordance with a further preferred embodiment, the receding process results in complete elimination of an overlap region between two strip sections of adjacent rows.
In FIGS. 1a-f, identical reference symbols designate identical or functional identity constituent parts.